Standard IC operating input logic high and low voltage levels (VIH and VIL) have been set by industry standards. For DRAM devices in the CMOS family, such levels are typically 0.8 volts plus or minus 100 millivolts for VIL and 2.4 volts plus or minus 100 millivolts for VIH. TTL trip points are usually 2 volts for VIH and 0.8 volts for VIL. In other words, as the input voltage increases to 2 volts and higher, the input is interpreted as a high logic level. As the voltage decreases to 0.8 volts and lower, the input is interpreted as a low logic level. The input signal is subject to noise from other lines via parasitic capacitances and leakage currents, so it is important that the trip points do not drift into the range where false highs or lows may be perceived. TTL logic, however may operate at the mercy of voltage supplies that may vary from less than three volts to at least 7.5 volts which is commonly used for high voltage testing. This varying power supply voltage makes it difficult to ensure that the input will be interpreted by an input buffer as the intended input. In one instance, a VCC supply change from 2.7 Volts to 3.9 Volts resulted in a shift of TTL input trip points in a range of from 490 millivolts to 590 millivolts. There is a need for an input buffer which is able to determine whether an input signal is intended as a high input signal logic level, or a low input signal logic level, even when the VCC voltage level changes.
One prior solution can be seen in U.S. Pat. No. 5,278,460, to Casper. It essentially regulates the voltage supplied to the input buffer by using a voltage variable transistor in series between the supply and the input buffer. As VCC changes, the voltage across the transistor also changes with the change in VCC, effectively keeping the voltage supplied to the input buffer fairly constant The input buffer comprises an input inverter for receiving the signals and detecting and inverting intended high or low logic levels, and a second inverter for converting the logic levels back to the desired polarity. There is a need for a way to compensate for supply voltage changes without trying to control the voltage supply to the input buffer, while providing stable trip points over drastic changes in supply voltage.